Flash memory devices are nonvolatile semiconductor memory devices capable of storing data in the absence of power. For example, a flash memory device may program an erase state (e.g., a ‘1’ state) into a program state (e.g., a ‘0’ state) on a 1-byte basis. The flash memory device must program new data after erasing old data on a block basis.
In a system including a typical flash memory device, a RAM is located outside the flash memory device and is connected through an external bus to the flash memory device. Thus, an operation of updating data stored in the flash memory device can require an operation of copying data from the flash memory device into the RAM, an operation of erasing the flash memory, and an operation of re-programming updated data from the RAM into the flash memory device.
FIG. 3 is a block diagram of a typical nonvolatile semiconductor memory system. Referring to FIG. 3, a nonvolatile semiconductor memory system 100 includes a nonvolatile semiconductor memory device 101 and a micro processing unit (MPU) 105. The nonvolatile semiconductor memory 101 includes a memory region and a controller 103. The memory region is divided into blocks and used to store data. The data stored in the memory region are updated on a block basis. The controller 103 controls an overall operation of the nonvolatile semiconductor memory device 101. For example, the controller 103 determines whether the state of each cell in a block 102 of the memory region is in a program state (e.g., a ‘0’ state) or in an erase state (e.g., a ‘1’ state).
The MPU 105 is connected to the nonvolatile semiconductor memory device 101. The MPU 105 includes a processor 106 and a RAM 107. It will be readily understood that the RAM 107 is not limited to being included in the MPU 105. For example, the RAM 107 may be located outside the MPU 105 and the nonvolatile semiconductor memory device 101.
The processor 106 is connected to the controller 103 of the nonvolatile semiconductor memory device 101. The processor 106 communicates with the controller 103 to control a data updating operation. For example, the processor 106 provides an erase start command to the controller 103. In response to the erase start command, data of the block 102 including update data of the nonvolatile semiconductor memory device 101 are copied into the RAM 107. The data copied into the RAM 107 are updated in the RAM 107.
FIG. 4 is a flow chart illustrating a typical operation of updating data stored in the nonvolatile semiconductor memory device 101. Referring to FIG. 4 in step S101, the processor 106 copies all the data of the block 102 in the memory region of the nonvolatile semiconductor memory device 101, which includes update data, into the RAM 107 located outside the nonvolatile semiconductor memory device 101. For example, the RAM 107 may be included in the MPU 105. In step S102, the processor 106 updates only an update data portion of the data copied into the RAM 107. In step S103, the processor 106 controls the controller 103 to erase the corresponding block 102 of the memory region of the nonvolatile semiconductor memory device 101. The processor 106 re-programs all the block data, which include the data updated in the RAM 107, into the corresponding block 102 of the memory region of the nonvolatile semiconductor memory device 101.
FIG. 5 is a flow chart illustrating the erase operation of step S103 illustrated in FIG. 4. Referring to FIG. 5, the erase operation includes a pre program operation, an erase operation, and a post program “threshold voltage adjust” operation. In the pre program operation, the controller 103 programs all the cells having an erase state (e.g., a ‘1’ state) into a program state (e.g., a ‘0’ state). In order to perform this operation, the controller 103 checks (e.g., verifies) whether the state of each cell is in a program state or an erase state, sequentially from the first address of the corresponding block 102, in step S301. Thereafter, in step S302, the erase operation proceeds according to the checked cell state. If the cell state is a program state (NO), the erase operation proceeds to step S304. If the cell state is an erase state (YES), the erase operation proceeds to step S303.
In step S303, the controller 103 applies a program stress (e.g., a program voltage) to the cell having an erase state to thereby program the corresponding cell. In step S304, the controller 103 determines whether the pre program operation is performed up to the last address in the block 102. If the pre program operation is not performed up to the last address in the block 102 (NO), the controller 103 returns to step S301 to perform a pre program operation on the next address. If the pre program operation is performed up to the last address in the block 102 (YES), the controller 103 performs an erase operation of step S305.
In step S305, the controller 103 erases all the cells of the block 102 (i.e., performs a “flash” erase) and checks (e.g., verifies) whether the erase operation is normally performed. When the erase operation is completed, a post program operation of step S306 is performed.
The post program operation is an operation that adjusts and equalizes the minimum physical voltage (e.g., threshold voltage Vth) of all the erased cells of the block 102. For example, in step S306, the controller 130 equalizes the minimum physical voltage (e.g., threshold voltage Vth) of each cell by applying a post program stress (e.g., a post program voltage) to each cell sequentially from the first address in the block 102. Then, the controller 103 checks (e.g., verifies) whether the cell is programmed to the minimum physical voltage (e.g., threshold voltage Vth).
Thereafter, in step S307, the controller 103 determines whether the post program operation (i.e., the equalization of the minimum physical voltage (e.g., threshold voltage Vth) is performed up to the last address in the block 102. If the post program operation is not performed up to the last address in the block 102 (NO), the controller 103 returns to step S306 to perform a post program operation of the next address. If the post program operation is performed up to the last address in the block 102 (YES), the controller 103 ends the post program operation. That is, the controller 103 ends the erase operation (i.e., step S130 of FIG. 4).